In a conventional computer, data-driven processors capable of performing parallel processing without causing overhead have been developed. The aforementioned data-driven processor is designed based on data-driven principles that enable each instruction in a program to be executed at time at which all pieces of its required input data are prepared. As technology using such data-driven principles, technologies disclosed in the following Patent documents 1 and 2 are known in the prior art.
Patent document 1 (Japanese Patent Application Publication No. 2004-13602) discloses a configuration in which a data-driven processor has a plurality of processing elements (PE's), and packets that convey partitioned data are input to the respective processing elements (PE's). In the configuration described in Patent document 1, a processing element (PE) includes a firing control unit (FC), a functional processor unit (FP), a program storage unit (PS), etc., and the firing control unit (FC) is able to determine whether all packets required to execute an instruction have been prepared based on input packets. If all packets have been prepared, firing conditions are considered to be satisfied, the packets from the firing control unit (FC) are transmitted to the functional processor unit (FP) to perform an operation, and packets having the results of the operation are transmitted to the program storage unit (PS). In compliance with the transmitted packets and a new instruction designated in instruction memory (IM), the program storage unit (PS) generates packets based on the new instruction and transmits the packets to another processing element (PE) which is a designated destination.
Further, Patent document 1 describes that each processing element (PE) has a super-pipeline structure based on a self-timed elastic pipeline. That is, the respective function blocks of the firing control unit (FC), the functional processor unit (FP), and the program storage unit (PS) which are in the processing element (PE), are configured in multiple pipeline stages. Further, each pipeline stage is provided with a data latch (DL) for maintaining packets, a logic circuit (LC) for processing the maintained packets, and a self-timed transfer control mechanism (STCM) for providing a synchronization signal (clock signal and trigger signal) to the data latch. Further, in each pipeline stage, transmission timing of packets is autonomously determined depending on the states of upstream and downstream pipeline stages (data is empty or being processed) in a packet flow.
Patent document 2 (Japanese Patent Application Publication No. 2005-108086) discloses technology relating to a data-driven processor. An invention described in Patent document 2 discloses a configuration in which each processing element (PE) connected via a first switch (SW1) can process data-driven packets processed in parallel in compliance with instructions issued based on the data dependencies among them and control-driven packets sequentially processed in compliance with instructions sequentially issued based on a program counter, in the same pipeline.
Each processing element (PE) described in Patent document 2 has an instruction fetch unit (IF) for fetching an instruction based on input packets, an instruction decode unit (ID) for decoding the instruction fetched and issued by the instruction fetch unit (IF), a second switch (SW2) for causing the instruction output from the instruction decode unit (ID) to branch, a firing control unit (FC) for determining firing conditions based on the packets transmitted from the second switch SW2, an execution unit (EX) for executing the instruction (calculation of values, reading/writing from/to memory, calculation of addresses or branch destinations, etc.) based on the packets transmitted from the firing control unit (FC) if the firing conditions are satisfied, and a write back unit (WB) for, if the instruction processed by the execution unit (EX) is a control-driven instruction for branch calculation or the like, performing writing to a register (REG).
Patent document 3 (Japanese Patent Application Publication No. 2010-20598) discloses the use of autonomous decentralized communication network (ad hoc network) and data-driven processor so as to reduce power consumption in a networking system, in addition, the technology that controlling the supply of power to pipeline stages such that, when neither processing nor data latching (data maintenance) are performed in a downstream pipeline stage, the supply of power is stopped, and when processing is not performed and only data latching is performed in a downstream pipeline stage, only a minimum voltage is applied.
Patent document 4 (Japanese Patent Application Publication No. 2011-30210) discloses technology for counting the number of transmission-waiting packets corresponding to a transmission queue, setting a probability that a message will be relayed by comparing the number of transmission-waiting packets with a threshold value, and setting a waiting time required to wait for relay based on the results of the comparison, then processing relay based on the set probability and waiting time, in order to check the load state of the node and perform a flooding function enabling the relay of data to be efficiently executed, for each node constituting the network.